View LC89515K_278538.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Ordering number : EN4272C
CMOS LSI
LC89515K
CD-ROM/CD-I Error Correction/ Host Interface LSI
Overview
The LC89515K is a version of the LC8951 in which certain aspects of the internal registers have been improved to make them even easier to use in CD-ROM and CD-I products. The basic blocks are identical to those in the LC8951 and these products are software and pin compatible. Thus this product can replace the LC8951 without change. (However, this product is provided in a slightly different package: a short lead type QIP-80E as opposed to the QIP-80A.) The LC89515K is an error correction and host interface LSI for use in CD-ROM and CD-I products. This product integrate in a single chip all CD-ROM specific functions, including the error correction that was previously implemented in software on a microprocessor and the CD player and host computer interfaces that were previously implemented in discrete components or gate arrays. The use of the LSI can provide significant improvements in CD-ROM and CD-I players, including increased transfer rates, miniaturization, increased reliability, an improved cost performance ratio, and a more efficient development period.
Package Dimensions
unit: mm 3174-QFP80E
[LC89515K]
SANYO: QIP80E
Features
* Software and pin compatibility with the LC8951 (Changes were made to internal registers, the SRAM interface, and other aspects.) * Support for CD-ROM (mode 1) and CD-I (mode 2, forms 1 and 2) * All CD-ROM/CD-I special functions implemented on a single chip * Hardware error detection and correction for high speed, without relying on software * Real-time error correction: Error correction and detection are possible without interrupting the host interface bus. * Fast transfers: up to 2.3 MB/s (18.4 Mb/s) * Support for low-speed hosts (multiple block buffering) * Built-in host interface command FIFO (for easy SCSI support) * Built-in 12-byte status FIFO * CMOS circuits, single 5 V power supply
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
O2095HA (OT)/12395TH (OT)/ 61394TH No. 4272-1/6
LC89515K System Block Diagram
Pin Assignment
Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, NC: No connection Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 VSS RA6 RA7 RA8 RA9 RA10 RA11 RA12 RA13 RA14 RA15 RWE VSS ROE ERA IO8 IO7 IO6 IO5 IO4 IO3 IO2 IO1 VSS XTALCK XTAL TEST1 Pin Type P O O O O O O O O O O O P O B B B B B B B B B P I O I Pin No. 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 40 51 52 53 54 TEST2 CSEL LMSEL VDD LRCK SDATA BCK C4LR C2PO MCK D0 D1 D2 VSS D3 D4 D5 D6 D7 RS RD WR CS INT VSS RESET ENABLE Pin Type I I I P I I I I I O B B B P B B B B B I I I I O P I I Pin No. 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 HWR HRD CMD WAIT DTEN STEN EOP RCS HDE VSS HD7 HD6 HD5 HD4 HD3 HD2 HD1 HD0 VDD SELDRQ RA0 RA1 RA2 RA3 RA4 RA5 Pin Type I I I O O O O O O P B B B B B B B B P I O O O O O O
Note: Do not leave any of the VDD or VSS pins open. All of the VDD and VSS pins must be connected to ground or the power supply, respectively.
No. 4272-2/6
LC89515K Block Functions The LC89515K consist of three major blocks. This section describes those blocks. 1. CD Player Interface and Data Input Block This LSI can handle three serial input formats selectable by setting external pin voltages. That is, differences in CD player serial data formats can be compensated for by setting the CSEL and LMSEL inputs. Internal operations are synchronized with the input data in block (sector) units using a synchronization detector circuit. The synchronization circuit not only uses pattern detection on the externally input data, but also performs synchronization protection with a synchronization signal interpolation circuit. These two synchronization systems can be turned on or off under program control. The input data is written to a buffer RAM in 8-bit units after passing through a descrambling circuit. The C2 pointer (error flag) from the CD player is also written to RAM at this time. Although applications that use the C2 pointer must provide a 9-bit RAM, the C2 pointer may be omitted and such applications need only provide an 8-bit RAM. However, note that erasure correction cannot be performed if the C2 pointer is not used. All input data, including sync, header, subheader and parity (2352 bytes) is stored in RAM in the order received from the CD player in its entirety. Furthermore, the LC89515K provides an output pin (MCK) for use with the CD LSI's oscillator input pin. Therefore, the number of oscillator elements in the end product can be reduced by selecting the LC89515K master clock frequency to be twice the CD LSI clock frequency. 2. Error Detection and Correction Block Error correction code decoding is performed after a full block (sector: 2352 bytes) of data has been stored in RAM. The LC89515K error correction function operates in real time completely internally. The system software merely waits for that processing to complete. Furthermore, buffering of data from the CD and transfer to the host computer are performed simultaneously. That is, the LC89515K can transfer to the host computer data that has been error corrected without any reduction in the data transfer rate from the CD. The error correction technique not only consists of error detection and correction, but also supports combination with erasure correction referencing the C2 pointer. This means that data with high reliability is acquired. The error detection and correction process can correct single symbol errors, and can correct two symbol errors when combined with erasure correction. Furthermore, the error correction algorithm is programmable, and the LC89515K can be instructed to perform a wide variety of procedures, such as iterative correction or QP/PQ correction, to improve data reliability. After decoding the error correction codes (ECC), a 32-bit CRC error check is performed using the error detection codes (EDC). During the CRC check the header and subheader are loaded into LC89515K internal registers. After completing the CRC check the LC89515K issues a decoding complete interrupt to the control microprocessor. The microprocessor then reads the header and subheader of the decoded block, the start address of the block in buffer RAM, and a decoding result status indicator from the LC89515K. 3. Host Interface Block The data transfer rate to the host computer has been improved significantly, to 2.3 MB/s, and since the amount of buffering RAM has been increased to 64 kB, up to 27 sectors (blocks) of the CD ROM drive can be stored. This memory can also be used as a disk cache memory. The host interface provides an 8-byte FIFO for receiving commands from the host. The host can write up to 8 bytes of commands at one time by asserting the HWR signal. When the host writes to the FIFO, the LC89515K issues a command interrupt to the control microprocessor. Here, the commands written to the 8-byte FIFO are never interpreted by the LC89515K. When transferring data to the host, the control microprocessor writes the number of bytes to transfer and the start address in buffer RAM of the block to be transferred. Then, it performs a write operation to the transfer start trigger register. This causes the DTEN pin to go low and informs the host of the data transfer start. While the DTEN pin is low the host reads data items one after another by generating HRD read pulses. If the host reads extremely rapidly, i.e., over about 2.3 MB/s, then the LC89515K will output a WAIT signal. The host must not set HRD high while WAIT is low. During this single block transfer operation, the microprocessor does nothing other than waiting for the transfer complete interrupt that occurs when the transfer is done.
No. 4272-3/6
LC89515K Furthermore, the LC89515K SELDRQ pin can be used to perform DRQ (data request) transfers. This is a technique in which transfers are performed by the host outputting HRD pulses according to a data request signal output from the LC89515K and is similar to DMA controller operation. When the last byte of the count specified by the control microprocessor is read, EOP goes active while the read pulse is output. Also DTEN is set inactive after this time. Next, a transfer complete interrupt is issued to inform the control microprocessor that the transfer to the host has completed. The LC89515K control microprocessor can pass the decoding result for the data requested by the host and the CDROM drive status information to the host by writing to the LC89515K internal status registers. The status registers are a 12-byte FIFO, and the host reads out data while the STEN signal is low. The STEN signal goes high when the last byte is read. The LC89515K has nothing to do with the content of the status registers. Since the command and status registers are neither interpreted nor executed by the LC89515K, the LC89515K user can define the command and status data as unrestricted protocols between the host and the microprocessor. This allows CD-ROM application systems to be designed without restriction, and also allows an existing system to be replaced by a system using the LC89515K. 4. Points Common to All Blocks The LC89515K performs data input and decoding at the same time in a pipelined manner. Also, writes of input data to the buffer RAM, writes of data to be decoded, and reads to the buffer RAM for transfers to the host all proceed at the same time with synchronization always being maintained by the LC89515K. Therefore there is no need for the control microprocessor to be concerned with which master (system block) is accessing the buffer RAM. 5. Register Table Read
RS 0 AR -- 0000 0001 0010 0011 0100 0101 0110 1 0111 1000 1001 1010 1011 1100 1101 1110 1111 No. -- R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 Symbol AR COMIN IFSTAT DBCL DBCH HEAD0 HEAD1 HEAD2 HEAD3 PTL PTH WAL WAH STAT0 STAT1 STAT2 STAT3 BIT7 0 msb CMDI B7 DTEI msb msb msb msb A7 A15 A7 A15 CRCOK MINERA RMOD3 VALST BIT6 0 -- DTEI B6 DTEI -- -- -- -- A6 A14 A6 A14 ILSYNC SECERA RMOD2 WLONG BIT5 0 -- DECI B5 DTEI -- -- -- -- A5 A13 A5 A13 NOSYNC BLKERA RMOD1 CBLK BIT4 0 -- 1 B4 DTEI -- -- -- -- A4 A12 A4 A12 LBLK MODERA RMOD0 BIT3 A3 -- DTBSY B3 B11 -- -- -- -- A3 A11 A3 A11 WSHORT SH0ERA MODE BIT2 A2 -- STBSY B2 B10 -- -- -- -- A2 A10 A2 A10 SBLK SH1ERA NOCOR BIT1 A1 -- DTEN B1 B9 -- -- -- -- A1 A9 A1 A9 ERABLK SH2ERA RFORM1 BIT0 A0 lsb STEN B0 B8 lsb lsb lsb lsb A0 A8 A0 A8 UCEBLK SH3ERA RFORM0
Note: The values of the shaded bits are ignored.
No. 4272-4/6
LC89515K Write
RS 0 AR -- 0000 0001 0010 0011 0100 0101 0110 1 0111 1000 1001 1010 1011 1100 1101 1110 1111 No. -- R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 Symbol AR SBOUT IFCTRL DBCL DBCH DACL DACH DTTRG DTACK WAL WAH CTRL0 CTRL1 PTL PTH CTRL2 RESET A7 A15 DECEN SYIEN A7 A15 0 SYDEN A6 A14 0 A6 A14 A5 A13 E01RQ DSCREN A5 A13 0 A4 A12 AUTORQ COWREN A4 A12 BCKSL A3 A11 ERAMRQ MODRQ A3 A11 DLAEN A2 A10 WRRQ FORMRQ A2 A10 0 A1 A9 QRQ MBCKRQ A1 A9 STENCTL A0 A8 PRQ SHDREN A0 A8 STENTRG A7 A15 A6 A14 A5 A13 A4 A12 msb CMDIEN B7 -- DTEIEN B6 -- DECIEN B5 -- CMDBK B4 BIT7 BIT6 BIT5 BIT4 BIT3 A3 -- DTWAI B3 B11 A3 A11 BIT2 A2 -- STWAI B2 B10 A2 A10 BIT1 A1 -- DOUTEN B1 B9 A1 A9 BIT0 A0 lsb SOUTEN B0 B8 A0 A8
Note: The values of the shaded bits are ignored.
6. Additional Registers Write [R14] CTRL2: Control 2 STENCTL (STEN control) 0.........The external STEN pin goes to 0 when the microprocessor writes one byte of status information. (This is identical to LC8951 operation.) 1.........The external STEN pin goes to 0 due to 0 being written to the STENTRG register when the microprocessor writes * bytes of status information. This bit is set to 0 on reset. STENTRG (STEN trigger) This bit is only valid when STENCTL is 1. The external STEN pin goes to 0 when a 0 is written to this bit. This bit is reset when the host reads the last byte, i.e., when the external STEN pin has become 1. DLAEN (drive last address enable) When WRRQ is set to 0 during buffering, buffering continues until the next SYNC signal arrives and then stops. This results in the sectors that are buffered when WRRQ was set to 0 becoming valid. (This bit is set to 0 on reset.) BCKSL (bit clock select) Setting this bit to 1 allows the bit clock from the CD-DSP to be inverted. (SDATA is acquired on the rising edge of BCK.) (This bit is set to 0 on reset.)
No. 4272-5/6
LC89515K
Specifications
Absolute Maximum Ratings at VSS = 0 V
Parameter Maximum supply voltage I/O voltages Allowable power dissipation Operating temperature Storage temperature Soldering temperature Symbol VDD max VI, VO Pd max Topr Tstg 10 seconds Ta = 25C Ta = 25C Ta 70C Conditions Ratings -0.3 to +7.0 -0.3 to VDD + 0.3 350 -30 to +70 -55 to +125 260 Unit V V mW C C C
Allowable Operating Ranges at Ta = -30 to +70C, VSS = 0 V
Parameter Supply voltage Input voltage range Symbol VDD VIN Conditions min 4.5 0 typ 5.0 max 5.5 VDD Unit V V
Electrical Characteristics DC Characteristics at Ta = -30 to +70C, VSS = 0 V, VDD = 4.5 to 5.5 V
Parameter Input high level voltage Input low level voltage Input high level voltage Input low level voltage Output high level voltage Output low level voltage Output low level voltage Input leakage current Pull-up resistance Symbol VIH1 VIL1 VIH2 VIL2 VOH VOL1 VOL2 IL RUP Conditions All input pins except those in (1) below and XTALCK (1) RESET (Schmitt trigger), RD, WR, HRD, HWR, CMD, CS, ENABLE and all bus pins IOH = -2 mA IOL = 2 mA IOL = 2 mA All output pins(including the bus pins) except those in (2) below and XTAL (2) INT (open drain circuit with pull-up resistor) min 2.2 0.8 2.5 0.6 2.4 0.4 0.4 -25 10 20 +25 40 typ max Unit V V V V V V V A k
VI = VSS, VDD: All input pins All bus pins, INT
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of February, 1997. Specifications and information herein are subject to change without notice. No. 4272-6/6

▲Up To Search▲

Price & Availability of LC89515K

	To Download LC89515K Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .